Fixed-value and Stem Unobservability Theorems for Logic Redundancy Identiication

There is a class of implication-based methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation ATPG but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a xed-value theorem and two theorems on fanout stem unobservability. We represent signal controllabilities and observabilities using an implication graph and its transitive closure TC. Both complete and partial implications are included. Weaknesses of this procedure a r e i n d e aling with the eeects of xed-valued variables on TC and the lack of observability relations across fanouts. The xed-value theorem adds unconditional edges from all variables to the xed variable and then recomputes TC recursively until no new xed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has xed values, or is unobservable. Results are c onsiderably improved f r om the previously reported implication-based identiiers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identiied.